RISC-V Reddit

assembly (mul and mulh)

for MUL rd,rs1,rs2, i know that mul returns the lower half bits of the product and it doesn’t matter whether rs1 and rs2 are signed or unsigned since the result will be the same. but does anyone know why? is there some sort of formal proof or general case that explains why it’s the same lower bits

https://redd.it/1kng2c6
@r_riscv

Reddit

From the RISCV community on Reddit

Explore this post and more from the RISCV community

www.tg-me.com/us/RISC V Reddit/com.r_riscv/3323

13 viewsMay 15 at 20:24

assembly (mul and mulh)

for MUL rd,rs1,rs2, i know that mul returns the lower half bits of the product and it doesn’t matter whether rs1 and rs2 are signed or unsigned since the result will be the same. but does anyone know why? is there some sort of formal proof or general case that explains why it’s the same lower bits

https://redd.it/1kng2c6
@r_riscv

BY RISC-V Reddit